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TECHNICAL DATA
IN74ACT174
Hex D Flip-Flop with Common Clock and Reset
High-Speed Silicon-Gate CMOS
The IN74ACT174 is identical in pinout to the LS/ALS174, HC/HCT174. The IN74ACT174 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of six D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active-low. * TTL/NMOS Compatible Input Levels * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 A; 0.1 A @ 25C * Outputs Source/Sink 24 mA
ORDERING INFORMATION IN74ACT174N Plastic IN74ACT174D SOIC TA = -40 to 85 C for all packages
PIN ASSIGNMENT LOGIC DIAGRAM
FUNCTION TABLE
Inputs Reset L PIN 16=VCC PIN 8 = GND H H H H X = Don't care L Clock X D X H L X X Output Q L H L no change no change
Rev. 00
IN74ACT174
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 50 50 750 500 -65 to +150 260
Unit V V V mA mA mA mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TJ TA IOH IOL tr, tf
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Junction Temperature (PDIP) Operating Temperature, All Package Types Output Current - High Output Current - Low Input Rise and Fall Time (except Schmitt Inputs)
*
Min 4.5 0 -40
Max 5.5 VCC 140 +85 -24 24
Unit V V C C mA mA ns/V
VCC =4.5 V VCC =5.5 V
0 0
10 8.0
VIN from 0.8 V to 2.0 V
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Rev. 00
IN74ACT174
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VIH VIL VOH Parameter Minimum HighLevel Input Voltage Maximum Low Level Input Voltage Minimum HighLevel Output Voltage Test Conditions VOUT=0.1 V or VCC-0.1 V VOUT=0.1 V or VCC-0.1 V IOUT -50 A VIN=VIH or VIL IOH=-24 mA IOH=-24 mA VOL Maximum LowLevel Output Voltage IOUT 50 A
* *
Guaranteed Limits 25 C 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 -40C to 85C 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 75 -75 8.0 80 A mA mA mA A V Unit V V V
V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 5.5 5.5 5.5 5.5 5.5
VIN=VIH or VIL IOL=24 mA IOL=24 mA VIN=VCC or GND VIN=VCC - 2.1 V VOLD=1.65 V Max VOHD=3.85 V Min VIN=VCC or GND
IIN ICCT IOLD IOHD ICC
Maximum Input Leakage Current Additional Max. ICC/Input +Minimum Dynamic Output Current +Minimum Dynamic Output Current Maximum Quiescent Supply Current (per Package)
*
All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time.
Rev. 00
IN74ACT174
AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits Symbol Parameter 25 C Min fmax tPLH tPHL tPHL CIN Maximum Clock Frequency (Figure 1) Propagation Delay, Clock to Q (Figure 1) Propagation Delay, Clock to Q (Figure 1) Propagation Delay, Reset to Q (Figure 2) Maximum Input Capacitance 165 1.5 1.5 1.5 4.5 10.5 10.5 9.5 Max -40C to 85C Min 140 1.5 1.5 1.5 4.5 11.5 11.5 11.0 Max ns ns ns ns pF Unit
Typical @25C,VCC=5.0 V CPD Power Dissipation Capacitance 85 pF
TIMING REQUIREMENTS(VCC=5.0 V 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits Symbol tsu th tw tw trec Parameter Minimum Setup Time, Data to Clock (Figure 3) Minimum Hold Time, Clock to Data (Figure 3) Minimum Pulse Width, Reset (Figure 2) Minimum Pulse Width, Clock (Figure 1) Minimum Recovery Time, Reset to Clock (Figure 2) 25 C 1.5 2.0 3.0 3.0 0.5 -40C to 85C 1.5 2.0 3.5 3.5 0.5 Unit ns ns ns ns ns
Rev. 00
IN74ACT174
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
EXPANDED LOGIC DIAGRAM
Rev. 00
IN74ACT174
N SUFFIX PLASTIC DIP (MS - 001BB)
A
Dimension, mm
16 9 B
Symbol A
MIN 18.67 6.1
MAX 19.69 7.11 5.33
1
8
B C
F L
D F
0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38
0.56 1.78
C -T- SEATING
PLANE
G H
H J
N G D 0.25 (0.010) M T K M
J K L M N
10 3.81 8.26 0.36
NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side.
D SUFFIX SOIC (MS - 012AC) Dimension, mm
A 16 9
Symbol A
MIN 9.8 3.8 1.35 0.33 0.4 1.27 5.72 0 0.1 0.19 5.8 0.25
MAX 10 4 1.75 0.51 1.27
H
B
P
B C
1
G
8 C R x 45
D F G
-TD 0.25 (0.010) M T C M K
SEATING PLANE
J
F
M
H J K M P R
8 0.25 0.25 6.2 0.5
NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side.
Rev. 00

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